15-25 MHz Fractional-N Synthesizer

Design Schematics Embedded CPU JAM STAPL Loop Filter Spectra MASH Simulation Back to projects

Underneath 1 |  Underneath 2

This fractional-N synthesizer covers 15 to 25 MHz in 1 Hz steps. Most of the work is done by the 128-macrocell CPLD which hosts the reference and VCO dividers, phase-frequency detector, and a primitive 8-bit CPU. The VCO divider is controlled by a 4th-order 32-bit MASH. MASH computations are performed by the CPU. Data and instructions are stored off-chip in a static RAM which is pre-loaded, via the JTAG interface, from an attached PC.

If you're not familiar with fractional-N synthesis, or the term MASH, the basic principle is that by frequently changing the PLL division ratio, the MASH controls the synthesizer output frequency with extremely high resolution; the step size is very small. You'll find more about it, and links to other articles, on my first fractional-N synthesizer page. For a mathematical treatment, try the MASH theory page.

I wanted to be more ambitious in this, my second fractional-N synthesizer project. My previous design had a tuning sensitivity of only 4 KHz/volt, which made things a lot easier. Here, I'm using a VCO with a tuning sensitivity of 2.5 MHz/volt; even a few tens of nano-volts of noise on the VCO tuning line would produce severe FM sidebands / phase noise.

Another objective for this project was to evaluate the AD9901 type dead-band-free phase-frequency detector (PFD) as recommended by Oleg Skydan[1]. This becomes an XOR-gate type phase detector once the signals are close in frequency. It has no cross-over region, and is therefore highly linear around zero phase error. The action of the MASH produces predominently high frequency noise at the PFD output, which is removed by the loop filter. Any non-linearity in the PFD could produce low-frequency intermodulation products which would not be removed.

A third objective was to try a full 32-bit fourth-order MASH. Previously, despite using a larger CPLD, I only managed to squeeze-in a 16-bit MASH. This time, with a higher output frequency, and more clock cycles to play with, it was possible to serialise the MASH processing. Obviously, I had to take the storage off-chip: four 32-bit accumulators alone would use up 128 macrocells! The idea of using stored program control evolved from this requirement. The embedded CPU has 7 unconditional instructions.

Perhaps this project's most novel feature is the use of JamTM Standard Test and Programming Language (STAPL) to download stored program and initial MASH starting values into the attached SRAM: there are few examples of Jam STAPL on the web. Intended for in-circuit testing, it permits direct (albeit slow) access to CPLD I/O pins from the PC. The entire boundary scan register (288-bit for EPM7128) is serially loaded.


CPLDAltera EPM7128SLC84-15 (128 macrocells)
VCOMini-Circuits POS-25
XTAL Reference10 MHz
Comparison frequency †100 KHz (XTAL ÷ 100)
Fractional accumulator modulus   232 (32-bit)
Step size ††1 Hz
Output frequency15 - 25 MHz
Output level+2 dBm
Peak phase noise †††-78 dBc/Hz @ 500 Hz offset

÷M is programmable (66 ≤ M ≤ 128)
†† Arbitrary. MASH resolution is 100 KHz / 232 = 23µHz !
††† See spectra

CPLD top-level block

The reference divide-by-M, phase frequency detector, VCO divide-by-N, and MASH are all implemented in the CPLD:

The SR flip-flops power-up and initially remain LOW: inst2 holds the CPU in reset; inst6 stops the VCO divider. Using JTAG boundary scan, the I/O pins are hijacked by a JAM STAPL program, which downloads data and stored program into the SRAM, and asserts TRIG to kick things off. Internal logic remains operative in boundary scan mode. The CPU starts executing the stored program from address 0x80, and Reference Divider Modulus is latched, on the release of TRIG.

The CPU halts at the end of the program, END is asserted, and the next VCO divider (N+ΔN) is available at the N[7..0] output. Delayed by inst9 for one clock, the cout signal of the VCO Divide-by-N loads the next N+ΔN into the counter and restarts the CPU. Possibly due to a documented bug in Altera's lpm_counter mega-function, cout oscillates if it is directly fed back to sload. I haven't applied the Quartus service pack.

The length of the stored program, which must run to completion before the VCO divider overflows, constrains the minimum output frequency. The program is 73 instructions long and executes in 146 cycles; since -7 ≤ ΔN ≤ +8, the minimum output frequency is 154 times the comparison rate. The CPU is quiescent (static) when critical clock edges occur at the PFD.

AD9901-type PFD

The reference and VCO inputs are halved in frequency by toggling flip-flops. The divided clocks, which have a 50% duty-cycle, are forced into quadrature by the XOR-gate phase detector. Under lock, inst12 and inst13 remain static, and the XOR is permanently gated through to the output. If either input receives a second pulse before the other, inst12 and inst13 steer the VCO towards the XOR's capture range.

Unlike the conventional dual-DFF circuit, this phase detector has no dead-band; it is highly linear around zero phase error. Since the output is a square-wave, it contains significant energy at the reference frequency, and may require more filtering than a tri-state PFD; however, this is less of a handicap for a Fractional-N synthesizer, since the phase error is rarely zero in any case.


Synth2.qar  Right-click and Save-Target-As to download a Quartus archive of the CPLD design files (size 104k).

See also

My new 38-76 MHz Fractional-N Synthesizer using a Spartan-3 FPGA.


Externally Induced VCO Phase Noise Dennis Colin; Micronetics Wireless; Hudson, NH.


1. An All Digital Fractional-N Synthesizer O. Skydan, UR3IQO, QEX Nov/Dec 2003.
2. Fractional-N Synthesizers/PLLs FAQ SKYWORKS
3. Basics of Dual Fractional-N Synthesizers/PLLs SKYWORKS