15-25 MHz Fractional-N Synthesizer

Design Schematics Embedded CPU JAM STAPL Loop Filter Spectra MASH Simulation Back to projects

Stored program[1] Key Instruction Set
128 LDA 00152 STA 13176 ROT
129 ADD 01153 ADC 14177 STA 21
130 STA 01154 STA 14178 ROT
131 ADD 02155 LDA 15179 STA 22
132 STA 02156 ADC 16180 ROT
133 ADD 03157 STA 16181 STA 23
134 STA 03158 ADC 17182 ROT
135 ADD 04159 STA 17183 STA 24
136 STA 04160 ADC 18184 LDA 20
137 LDA 05161 STA 18185 ADD 21
138 ADC 06162 ADC 19186 ADD 22
139 STA 06163 STA 19187 ADD 23
140 ADC 07164 LDA 22188 ADD 24
141 STA 07165 STA 25189 SUB 25
142 ADC 08166 LDA 26190 SUB 26
143 STA 08167 STA 28191 SUB 26
144 ADC 09168 LDA 23192 SUB 27
145 STA 09169 STA 26193 SUB 27
146 LDA 10170 LDA 29194 SUB 27
147 ADC 11171 STA 30195 ADD 28
148 STA 11172 LDA 27196 ADD 29
149 ADC 12173 STA 29197 ADD 29
150 STA 12174 LDA 24198 ADD 29
151 ADC 13175 STA 27199 SUB 30
200 END
Integer  command (N) 8-bit
Fraction command (F) 32-bit
MASH Accumulators 32-bit
Accumulator overflows 1-bit
Delay D-flops 1-bit
Multiplier weights

Data memory map

00 01 02 03 04
05 06 07 08 09
10 11 12 13 14
15 16 17 18 19
20 21 22 23 24
25 26 27
28 29
30

ΔN

+1 +1 +1 +1
-1 -2 -3
+1 +3
-1
000aaaaaLDA  Load accumulator
001aaaaaSTA  Store accumulator
010aaaaaADC*†Add with carry[2]
011aaaaaADD* Add
100aaaaaSUB  Subtract
101xxxxxROT*†Shift carry into accumulator[2,5]
110xxxxxEND  Halt[3,4]
aaaaa = Address = Affected by carry[2]
xxxxx = Don't care* = Affects carry[2]

Minimal 8-bit CPU Architecture
1-operand memory-accumulator model; 8-bit instruction: 3-bit opcode, 5-bit address; 32 bytes of addressable data RAM.

Notes :
1. Program memory starts at address 128
2. The "carry" is a 4-bit shift register
3. Program restarts on VCO divider overflow
4. Next VCO divisor (N+ΔN) taken from accumulator
5. Accumulator 0000000C where C = shift register output

Carry propogation examples :
Carry-out from ADD at 129 is carry-in to ADC at 138.
Carry-out from ADC at 156 is saved in memory at 177.

Above is the programmer's quick reference guide to this processor. Although other programs are possible (e.g. integer-N mode, lower-order MASH, shorter accumulators, single-accumulator un-compensated Fractional-N), this CPU was specifically designed to run the 73 instructions above. Executing once per comparison cycle, leaving the next VCO divisor (N+ΔN) in the accumulator, they implement a 4th-order 32-bit MASH.

Processor Core

Instructions are fetched and executed on alternate VCO clock cycles. The program above executes in 146 cycles. Cycle time depends on VCO output frequency! Accumulator instructions are pipelined to overlap with the following fetch cycle.

The CPU core is written in VHDL. The most interesting part is the fragment below, which manages the program counter (pc), instruction register (ir) and fetch/execute cycle:

    process(clock, sclr, fe, pc, op)
    begin
        if rising_edge(clock) then
            if (sclr = '1') then
                pc <= "0000000";
                fe <= '0';
            elsif (fe = '0') then
                fe <= '1';
                ir <= data;
            elsif (op /= OP_END) then
                fe <= '0'; 
                pc <= pc + 1;
            end if;
        end if;
    end process;

    op <= ir(7 downto 5);

    RamAddr <= "000" & ir(4 downto 0) when (fe='1') else "1" & pc;
Note: the "1" prepended to the program counter is fed through an LCELL to synchronise transitions on A7 with the other address lines.

Wrapper

This block schematic "wrapper" interfaces the VHDL core to the SRAM data bus. This is the top-level "MASH" block:

It's essential to disable NOT Gate Push Back on LCELL inst10 and LCELL inst20 or else the tri-state transitions on OEL, OEH and the data bus will not coincide. RamAddr remains valid for 2ns after the rising-edge of WE, which is gated with the clock.

Simulation

I tested the CPU, and verified that SRAM timing requirements were met using the Quartus simulator:

OEL and OEH are tied together. One of them is always tri-state.

Pipelined Accumulator

The CPU accumulator is embedded as a component in the VHDL Core. This module is the lowest in the hierarchy:


To load the accumulator from memory, it is first cleared during the LDA execute cycle, and then summed with the operand pipeline register during the following fetch cycle. Pipelining is necessary to meet the 25 MHz VCO clock setup time through the adder.

In order to implement a 4th-order MASH efficiently, this CPU has 4 carry flags in a 4-bit FIFO shift register. The stored program updates the MASH accumulators, shown in the data memory map at the top of this page, a row at a time.