|Design||Schematics||Embedded CPU||JAM STAPL||Loop Filter||Spectra||MASH||Simulation||Back to projects|
Powered by regulator U1, which also supplies the +2.5V virtual-earth, HCT buffer U4 stops digital noise entering the loop. A HCT-family device was chosen, as VOH for this CPLD is a mere 3.2 volts. U4 is a single-gate SOT-23 surface-mount package. Note: 2.5V is right on the input voltage range limit for an AD797 on a single supply.
100µF decoupling capacitor C8 reduces low-frequency noise injection. Originally, the loop had insufficient bandwidth, and C8 significantly reduced close-in phase noise. A further improvement was replacing the original OP42 op-amp with the quieter NE5534. These effects would not have been so noticeable, if loop gain had been adequate in the first place.
The sinusoidal VCO output is converted to a square wave by a pair of HCU (unbuffered) CMOS inverters. The HCU04 has its own regulated supply. The buffer/limiter was the subject of much experimentation, as evidenced by the number of unused holes drilled around it. To minimise phase jitter, the CPLD clock must be driven across the logic threshold as quickly as possible. Rise-time at U6/C output, measured on a 100 MHz 'scope, is less than 4ns. A PNP differential pair using BF679S (fT=1GHz) was tried, but proved very slow. Preceding it with an MSA0404 MMIC (+8.3 dB gain) did not improve matters. High speed comparators (e.g. AD8561) were also considered, but not tried. You can't beat the simplicity of HCU gates!
The SRAM, CPLD and JTAG interface are powered, very inefficiently, using a 7805 in a TO-220 package bolted to the board, which drops 10 volts and dissipates nearly 2 Watts. This is the "dirty" 5V logic supply.
Since the embedded CPU is clocked by the VCO, the output is inherently immune to digital noise at this frequency. It is also coherent with the reference clock source, to which it is phase-locked.
TRIG starts (and restarts) the stored program after data is downloaded into the SRAM. The embedded CPU is held in reset while TRIG is asserted. The internal logic continues to function, but JAM STAPL has control of the device I/O pins.
In order to meet device timing requirements, two CPLD I/O pins are used to drive SRAM OE: OEH is either HIGH or tri-state; OEL is either LOW or tri-state. OE transitions coincide exactly with lo-Z to hi-Z and hi-Z to lo-Z impedance transitions on the data bus driver.
Pin 1 of the SRAM socket is actually soldered to the ground plane for mechanical support. CPLD address line A7 is connected to SRAM pin 22.
|Copyright © Andrew Holme, 2005.|