38-76 MHz Fractional-N Synthesizer

Back to projects All-surface-mount version locked to external standard 800 - 1600 MHz version


This fractional-N synthesizer covers 38 to 76 MHz in 1 Hz or smaller steps. Output is 3 dBm and phase noise is below -90 dBc/Hz at 100 Hz offsets. The VCO is a Mini-Circuits POS-75. The reference is a 3rd-overtone 100 MHz crystal oscillator. The reference and VCO dividers, 4th-order MASH and AD9901-style phase/frequency detector (PFD) are all implemented in a Xilinx Spartan-3 FPGA. PFD rate is 1 MHz. Output frequency is controlled over JTAG using a BSCAN_SPARTAN3 primitive in the FPGA. The circuit is constructed on a 2 layer PTH board with an almost continuous ground plane on the bottom. Smallest drill size is 0.5mm and minimum width/clearance is 0.2mm.

A project objective was to eliminate integer-N boundary spurs, from which my earlier 15-25 MHz fractional-N synthesizer suffered, by separating the VCO and reference frequency signals. These clocks must enter the FPGA sometimes only picoseconds apart. If they modulate each other's zero crossings (via ground bounce, supply dip or crosstalk) the resultant deterministic jitter appears as FM sidebands on the VCO at spacings related to the fractional frequency. More edges coincide when operating close to integer-N boundaries and low frequency modulation injected at the PFD is not removed by the loop. Happily, any such spurs are below the random phase noise level in this synthesizer.

Measures taken to isolate VCO and reference frequencies were:

In lock, the AD9901-style PFD outputs a 50% duty-cycle square wave. The VCO and reference events which toggle it are thus kept well apart. The FPGA must be quiet when these critical output-toggling clocks traverse it; but jitter can be tolerated at other times, provided counting is reliable. Conventional wisdom advises against placing jitter-sensitive analogue functions in an FPGA. Fortunately, the Spartan 3 is fully static and adds little random jitter. MASH computations are safely confined to "noisy" periods. In practical applications, external frequency control signals must also be synchronised to the PFD cycle.

Allowing time for the next state to ripple through four accumulators, the 4th-order MASH is clocked (on its own global clock net) a few VCO cycles before the VCO divider reloads with the new N+ΔN.

Placement of logic within the FPGA is constrained within the UCF file and must be verified using FPGA Editor.

PLL analogue schematic

Power supply filtering is elaborate. Q1 and Q2 provide "active decoupling" as recommended by Mini-Circuits to reduce linear regulator noise. Q1 emitter supplies a clean 3.3V for LVDS receiver U10. Q2 powers VCO U8. The 15V op-amp supply must be filtered; its PSRR alone is inadequate to suppress 100 Hz spurs due to full-wave-rectified hum on my bench supply.

This PLL exhibits a bandpass response, peaking around 1 KHz, to noise injected at the loop filter. A low-noise op-amp is essential. I planned to use the AD797; but its input voltage range does not extend to within 1.65V of the negative supply pin. I discovered this after making the PCB. The NE5534 works; but is also beyond datasheet limits. A good low-noise op-amp with rail-to-rail inputs is the LT1677. Phase noise was noticeably increased by the CA3140. A negative supply could be used; but the VCO V-TUNE input must never go negative.

All jitter-sensitive signalling in and out of the FPGA is on LVDS pairs. As can be seen in the photograph, wide tracks were required to achieve 100-ohm differential impedance on 1.6mm FR4. The PFD pair is correctly terminated by U10; however, the Spartan 3 does not support true differential termination and this was not realised in time to provide PCB lands for external termination resistors at the VCO and REF inputs. 100-ohm 0201 resistors could be fitted between the FPGA pins; but excellent results have been obtained without them!

May 2009 update: The poly layer loop filter integrator capacitor is slightly microphonic. Physically tapping C45 produces FM spikes of amplitude proportion to the DC tuning voltage which appears across this capacitor. I only discovered this after seeing it on a new all-surface-mount version of this board. I've since tried various capacitor types: ceramics are useless, film are better, tantalums are good; but only aluminium electrolytics are totally immune.

Output spectra

Phase noise is below -90 dBc/Hz and there is no trace of integer-N boundary spurs. This carrier is 1 KHz above a MHz boundary and close-in phase noise is below the 2382 noise floor on the right:

After rectifying a silly mistake, this performance was obtained on first powering and no attempt has yet been made to optimise it. Increasing the PFD rate and/or widening loop bandwidth might yield an improvement.

FPGA configuration

Spartan-3 configuration is loaded from a Xilinx XCF02 PROM using Master Serial Mode in which the FPGA drives CCLK. The internal oscillator is disabled after configuration:

Note: IO_L27N_4/DIN/D0 and IO_L31N_4/INIT_B are in bank 4 (VCCO_BOTTOM).

BSCAN_SPARTAN3 and platform USB

This primitive allows access to user-logic via the dedicated JTAG pins. I initially assumed SHIFT and UPDATE were clock enables with DRCK1 being the clock for the USER1 instruction; but that's not how it works. There's no pulse on DRCK1 for updates. I had to use UPDATE as a clock e.g.
   BSCAN_SPARTAN3 jtag (
      .DRCK1   (tck),
      .SHIFT   (shift), 
      .TDI     (tdi), 
      .UPDATE  (update)); 
   always @ (posedge tck)
      if (shift)
         {tdo,dr} <= {dr,tdi};

   always @ (posedge update)
      {N,F} <= dr;

This is the only way I could get it to work. There's very little on the web about this - what few examples I found all did the same.

ChipScope includes a Tcl-language JTAG API for Xilinx Platform USB cables, allowing user-logic to be controlled over the same cable that configured the FPGA. I downloaded a time-limited ChipScope evaluation to get this facility. It doesn't check the license file if you only use the JTAG functions. See ug029.pdf for a description of the Tcl API.

I have a Tcl script which accepts a parameter in Hertz, calculates the appropriate N.F command and sets the fractional-N synthesizer frequency. Annoyingly, there's a pipeline delay in there somewhere, presumably in the software, which means I have to execute the jtag_shiftdr twice!


May 2009 update

I've now developed an all-surface-mount version of this board. Designated Frac4, thanks to an improved loop filter (wider loop bandwidth and LT1677 op-amp) this has even lower phase noise than its predecessor. I don't yet know exactly how low because it's below the noise floor of my spectrum analyser; but I used my simulator to make a prediction.


The crystal oscillator (TCVCXO) is phase-locked to an external reference, permitting coherent operation. Locking to the ovened standard in my RACAL 9916 counter, measuring to 0.1 Hz accuracy on a 10-second gating interval, I can dial-up any number I want on the display.

There are two PLLs on this board: one for TCVCXO, another for the VCO. Both phase detectors and all dividers are implemented in the FPGA. As before, the timing of global clock edges is interleaved to prevent intermodulation between non-harmonically-related frequencies.

The VCO tuning sensitivity of 3.5 MHz per Volt is 3.5 Hz/µV. It's amusing to view a VCO output of 40.0000001 MHz whilst triggering off the external standard: the trace smoothly slides across the screen one cycle every ten seconds. Shift the frequency to 40 MHz and it stops dead. The VCO control voltage just dropped 29 nV. The Frac4 MASH accumulators work in BCD, allowing exact representation of decimal base 10 frequencies.

A narrow TCVCXO PLL bandwidth makes it a flywheel to clean-up noisy sources. By triggering a 'scope off the clean output, using a fast (1ns per cm) timebase, I see jitter of the TCVCXO and external source combined. This revealed some interesting things about my ancient test equipment and the much newer borrowed Agilient 53131A pictured above. The 10 MHz output of this counter runs all the time mains is present and is very clean when the counter is off; but I see deterministic jitter when I power it up! The 10 MHz STD OUT of my Marconi 2382 is quite clean but has sub-harmonics ('scope shows two sharp lines <100ps apart) and gives a little kick about once every 10 seconds.


This synthesizer covers 800 MHz to 1.6 GHz in 1 Hz steps using a Mini-Circuits ROS-1455+ VCO and Hittite Microwave HMC-363 divide-by-8 prescaler. Phase noise is too low to measure on a Marconi 2383 SA:

This is just a standard 1.6mm FR4 2-layer PTH board. The reverse is mostly continuous ground. Microwave nets are coplanar waveguides (CPW) with ground plane because these achieve 50-ohm impedance with narrow traces despite the 1.6mm board thickness. A large via underneath the HMC-363 divider allowed the ground paddle to be soldered from the back.

Reference frequency is derived from an experimental crystal oscillator, which is phase-locked to an external standard, or the standard can be used directly and the crystal oscillator disabled. Reference sources are converted to LVDS using half of a National LMH7324 ultra-high-speed quad comparator - the QFN package to the left of the FPGA.

Initially, VCO frequency found its way into the super-fast comparator, modulating zero-crossings and producing integer-N boundary spurs. Locking directly from an external reference, without the crystal oscillator, these spurs were greatly attenuated by increasing external drive level and adding filtering capacitors at the comparator inputs. Output spurious and phase noise thus obtained are too low to measure on a Marconi 2383 spectrum analyzer.

The experimental crystal oscillator did not work as well as hoped; and the impedance level of the output net feeding the comparator is too high, making it susceptible to pick-up of VCO frequency. Microwaves get around. The solution for next time will be a return to slower comparators!

March 2011 update: Frac5 is first LO and DSP-FPGA in experimental homemade GPS receiver