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The minimum step size of an integerN synthesizer equals the reference frequency (fREF). FractionalN synthesizers break this coupling; the steps can be very small indeed. Designers are free to increase comparison frequency and widen loop bandwidth  lock time is thus reduced; refererence spurs and microphonics are eliminated. Fractional spurs, however, are a new hazard.
FractionalN synthesizers work by periodically changing the division ratio from N to N+1 and back such that the average is N + F/M where 0≤F<M; N,F and M are integers. For example, if N is 5 for 99 cycles and 6 for one cycle, 5.01 is the average division ratio. An attached frequency counter would read 5.01 times fREF.
Unfortunately, there's a catch: switching the division ratio seriously disturbs the PLL resulting in a sawtoothlike waveform on the VCO control line and severe FM sidebands on the output. Fortunately, the disturbance is predictable  and various means have been devised to cancel it.
FractionalN synthesizers first appeared in the late 1960s and early 1970s. The earliest compensation schemes applied analogue correction to the VCO control line. A notable design was the synthesizer by Nigel King for the RACAL RA1792 communications receiver. A breakthrough came in 1984 when John Wells of Marconi Instruments invented an entirely digital scheme based on the principle of noise shaping.
Noise shaping concentrates the quantisation noise produced at the PFD output into the higher frequencies where it is removed by the lowpass filter. The loop structure is shown opposite.
The divider is controlled by a form of sigma delta modulator known as a MASH. The division ratio N+ΔN is not confined to N and N+1, it depends on the number of stages (order) of the MASH.
MASH output, ΔN, is a pseudorandom sequence. The VCO frequency is governed by the longterm mean of ΔN which is exactly F/M. Please visit my MASH Theory Page for a mathematical treatment.
The MASH structure is a series of firstorder sigma delta modulators, each fed by the quantisation error of the previous stage. ΣΔ modulators are widely used in A/D and D/A conversion, to achieve high resolution from fast low resolution (e.g. 1bit) converters by oversampling. The ΣΔ modulator is followed by a low pass filter. Conveniently, in A/D applications, it's a digital filter. A very readable retrospective on ΣΔ modulators can be found in chapter 3 of Ushaw^{[2]}.
My original plan was to use a Motorola MC145152 PLL controlled by a CPLD, but when I came across this article by Oleg Skydan, I realised I could implement the divider and phase frequency detector (PFD) in the CPLD. This simplified the hardware and offered the possibility to try different PFD designs.
The VCO centrefrequency was not important  this is an experimental design  I chose a low frequency to simplify construction. The VCO tuning range was kept to a minimum (100 KHz) to reduce the effect of noise on the VCO control line.
CPLD  Altera EPM7160SLC8410 (160 macrocells) 
XTAL Reference  8.192 MHz 
Comparison frequency  256 KHz (XTAL ÷ 32) 
Fractional accumulator modulus  65536 (16bit) 
MASH  4thorder 
Step size  1 KHz (MSB of F = Offset in KHz) 
VCO Frequency  4.3 MHz 
Output  +10 dBm 
Phase noise †  80 dBc/Hz @ 500 Hz offset; 100 dBc/Hz @ 1.5 KHz offset 
Discrete spurii  70 dBc @ 50 Hz (UK power line) 
^{†} See spectra.
ΣΔ modulation creates highfrequency energy at the PFD output. Any nonlinearity in the PFD can give rise to low frequency IMD products which are not removed by the LPF. Deadband is a form of nonlinearity. Imbalance between source and sink currents in the charge pump is another.
Mr Skydan implemented an AD9901 style ultralinear deadbandfree detector. This divides the PFD inputs by 2 and compares them using an XOR gate forcing the divided signals into quadrature. It is perfectly linear around Φ=0 because there is no crossover. I decided to keep this in reserve and try a conventional PFD with delayed reset first because I was rather wedded to my diode switching charge pump. I used an AD9901 style PFD in my 1525 MHz FractionalN Synthesizer.
The design is fully synchronous: VCO_IN is global clock GCLK1. The divided VCO sload is brought out as TEST_OUT to illustrate the spread of ΔN. DFF inst9 is necessary because lpm_counter0 oscillates if cout is fed straight back to sload. With this extra DFF delay, and since the countdown includes zero (e.g. 3,2,1,0,3,1,2,0....), lpm_constant0 is actually N2.
The CPLD is programmed insitu, via the PC parallel printer port, using a ByteBlaster cable connected to the 10way JTAG header.
4th Order 16bit MASH  Here's a link to a GIF image of the Quartus block schematic of the 4th order MASH. It's not large in bytes but it is in pixels which is why I haven't inlined it.  
3rd Order 8bit MASH  Here's an earlier version. It might be worth looking at this first because it's a bit simpler. Each accumulator has it's own adder. Note, however, this version was clocked by sload.  
Adder.v  Verilog code for calculating N+ΔN with signextension. This submodule is embedded in the MASH.  
Synth1.qar  Rightclick and SaveTargetAs to download a Quartus archive of the entire project (size 83k). 

PFD reset is taken offchip (via R5) thereby incurring a CPLD I/O delay. The 70 pF trimmer is there to explore the effect of adjusting the delay. Closein phase noise is noticeably reduced when the trimmer is fully meshed. The resultant delay is about 30 ns.
Discrete 1 KHz spurs around a 4353 KHz carrier (N=17, F=0x0100) were reduced by increasing C7 from 1n to 10n. The 1 KHz modulation (clearly visible on the VCO control line) could then be nulledout by adjusting VR1. The setting was quite critical. Only after doing this was the effect of the trimmer noticeable.
R4/C7 provide a pole at 720 KHz to prefilter fast edges before they reach the integrator opamp which has a gainbandwidth product of only 10 MHz. Arguably, C7 could be increased further. Alternatively, although I haven't tried this, a passive loop filter might be safer, followed by a low frequency opamp gain buffer. In the RA1792, RACAL used 22Ω / 100 pF and the AD518 opamp which also has a GBW 0f 10 MHz!
I chose a large value for FET biasing resistor R9 to make pinchoff the amplitude limiting mechanism. I kept C9 as small as possible to minimise loading on the tuned circuit.
The emitter follower operates in class A. The quiescent current must be sufficient to supply the peak load current.
FractionalN Synthesizers IFR (formerly Marconi Instruments) application note by David Owen.
An All Digital FractionalN Synthesizer O. Skydan, UR3IQO, QEX Nov/Dec 2003. Main TO3DSP site.
Behavioural Simulation of FractionalN Frequency Synthesizers and Other PLL Circuits Michael H. Perrott, MIT.
SigmaDelta FractionalN Frequency Synthesis Scott Meninger, MIT.
A FractionalN Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced QuantizationInduced Phase Noise Meninger and Perrott.
Model, Analyze, And Simulate ΣΔ FractionalN Frequency Synthesizers MICROWAVES & RF DECEMBER 2000.
A New Approach to FractionalN PLL Design APRIL 2003 MICROWAVE PRODUCT DIGEST.
PFD Deadzone aka deadband posted to sci.electronics.design
Copyright © Andrew Holme, 2004. 