Fractional-N Frequency Synthesizer

Design Spectra Loop Filter MASH Simulation Back to projects 15-25 MHz Synthesizer 38-76 MHz Synthesizer 800-1600 MHz Synthesizer


Underneath | CPLD Pinout

What is a fractional-N synthesizer?

The minimum step size of an integer-N synthesizer equals the reference frequency (fREF). Fractional-N synthesizers break this coupling; the steps can be very small indeed. Designers are free to increase comparison frequency and widen loop bandwidth - lock time is thus reduced; refererence spurs and microphonics are eliminated. Fractional spurs, however, are a new hazard.

Fractional-N synthesizers work by periodically changing the division ratio from N to N+1 and back such that the average is N + F/M where 0≤F<M; N,F and M are integers. For example, if N is 5 for 99 cycles and 6 for one cycle, 5.01 is the average division ratio. An attached frequency counter would read 5.01 times fREF.

Unfortunately, there's a catch: switching the division ratio seriously disturbs the PLL resulting in a sawtooth-like waveform on the VCO control line and severe FM sidebands on the output. Fortunately, the disturbance is predictable - and various means have been devised to cancel it.

Fractional-N synthesizers first appeared in the late 1960s and early 1970s. The earliest compensation schemes applied analogue correction to the VCO control line. A notable design was the synthesizer by Nigel King for the RACAL RA1792 communications receiver. A breakthrough came in 1984 when John Wells of Marconi Instruments invented an entirely digital scheme based on the principle of noise shaping.

Noise shaping concentrates the quantisation noise produced at the PFD output into the higher frequencies where it is removed by the low-pass filter. The loop structure is shown opposite.

The divider is controlled by a form of sigma delta modulator known as a MASH. The division ratio N+ΔN is not confined to N and N+1, it depends on the number of stages (order) of the MASH.

MASH output, ΔN, is a pseudo-random sequence. The VCO frequency is governed by the long-term mean of ΔN which is exactly F/M. Please visit my MASH Theory Page for a mathematical treatment.

The MASH structure is a series of first-order sigma delta modulators, each fed by the quantisation error of the previous stage. ΣΔ modulators are widely used in A/D and D/A conversion, to achieve high resolution from fast low resolution (e.g. 1-bit) converters by oversampling. The ΣΔ modulator is followed by a low pass filter. Conveniently, in A/D applications, it's a digital filter. A very readable retrospective on ΣΔ modulators can be found in chapter 3 of Ushaw[2].

Project objectives

Having built a PLL for ethernet clock recovery, where acquisition speed not output purity was important, I wanted to make a synthesizer with a clean output; I wanted to use the same diode switching technique in the charge pump as RACAL used in the RA1792 - because I think it's a neat circuit; and, I wanted to use a CPLD (Complex Programmable Logic Device). This project scratched all three itches.

My original plan was to use a Motorola MC145152 PLL controlled by a CPLD, but when I came across this article by Oleg Skydan, I realised I could implement the divider and phase frequency detector (PFD) in the CPLD. This simplified the hardware and offered the possibility to try different PFD designs.

The VCO centre-frequency was not important - this is an experimental design - I chose a low frequency to simplify construction. The VCO tuning range was kept to a minimum (100 KHz) to reduce the effect of noise on the VCO control line.

Specification

CPLDAltera EPM7160SLC84-10 (160 macrocells)
XTAL Reference8.192 MHz
Comparison frequency256 KHz (XTAL ÷ 32)
Fractional accumulator modulus   65536 (16-bit)
MASH4th-order
Step size1 KHz (MSB of F = Offset in KHz)
VCO Frequency4.3 MHz
Output+10 dBm
Phase noise †-80 dBc/Hz @ 500 Hz offset; -100 dBc/Hz @ 1.5 KHz offset
Discrete spurii-70 dBc @ 50 Hz (UK power line)

See spectra.

PFD Linearity

The conventional dual D-type flip-flop followed by charge pump can exhibit dead-band. This is a zone around Φ=0 in the middle of the transfer characteristic where the gain kPD falls to zero. It resembles crossover distortion and is caused by the charge pump transistors not switching on before the flip-flops are cleared. This can lead to increased close-in phase noise (jitter) because the loop simply stops working at very small phase errors. Delaying the PFD reset ensures that both charge pumps are fully switched on (before they switch off).

ΣΔ modulation creates high-frequency energy at the PFD output. Any non-linearity in the PFD can give rise to low frequency IMD products which are not removed by the LPF. Dead-band is a form of non-linearity. Imbalance between source and sink currents in the charge pump is another.

Mr Skydan implemented an AD9901 style ultra-linear dead-band-free detector. This divides the PFD inputs by 2 and compares them using an XOR gate forcing the divided signals into quadrature. It is perfectly linear around Φ=0 because there is no crossover. I decided to keep this in reserve and try a conventional PFD with delayed reset first because I was rather wedded to my diode switching charge pump. I used an AD9901 style PFD in my 15-25 MHz Fractional-N Synthesizer.

CPLD Programming

I used Altera's excellent Quartus II Web Edition 4.1 development software which is available from www.altera.com for free. Logic can be defined in Verilog or VHDL, but I mostly used the block editor which allows you to draw a schematic. Here's the top-level module. The MASH can be seen top left with N.F frequency command inputs. The Divisor[5..0] output is N+ΔN:

The design is fully synchronous: VCO_IN is global clock GCLK1. The divided VCO sload is brought out as TEST_OUT to illustrate the spread of ΔN. DFF inst9 is necessary because lpm_counter0 oscillates if cout is fed straight back to sload. With this extra DFF delay, and since the countdown includes zero (e.g. 3,2,1,0,3,1,2,0....), lpm_constant0 is actually N-2.

The CPLD is programmed in-situ, via the PC parallel printer port, using a ByteBlaster cable connected to the 10-way JTAG header.

Monster MASH

The EPM7160SLC84-10 CPLD has 160 macrocells which is just enough for a 4th order 16-bit (modulus 65536) MASH. To make it fit, I had to update the accumulators sequentially (over 4 clock cycles) using a shared 16-bit adder. Adders eat macrocells!

4th Order 16-bit MASH Here's a link to a GIF image of the Quartus block schematic of the 4th order MASH. It's not large in bytes but it is in pixels which is why I haven't inlined it.
3rd Order 8-bit MASH Here's an earlier version. It might be worth looking at this first because it's a bit simpler. Each accumulator has it's own adder. Note, however, this version was clocked by sload.
Adder.v Verilog code for calculating N+ΔN with sign-extension. This sub-module is embedded in the MASH.
Synth1.qar Right-click and Save-Target-As to download a Quartus archive of the entire project (size 83k).

PLL

Utilising Schottky barrier diodes for speed and Wilson current mirrors for balance, the charge pump is a little unusual! Q1, U3 form a Wilson mirror current source. Q2, U5 form a Wilson mirror current sink. Balance is assured because the programming currents (set by R2) are identical. I was unable to detect any difference between source and sink currents on my 3½-digit meter (1µA resolution). Theoretically, I wouldn't expect the match to be that good. More on this here.

 
BAT81 Quick Data (typical)
VF forward voltage 0.4 V
IR reverse current 10 nA
Cd diode capacitance 1.6 pF
The DC bias voltage at the centre of D2, D3 is set approximately midway between the high and low logic levels using preset VR1. When the flip-flops are cleared, D1 and D4 conduct, D2 and D3 are reverse-biased. A rising edge on DOWN_OUT shuts-off D1, D2 conducts, and 0.5mA flows into the integrator. A falling edge on UP_OUT switches the other diode pair and 0.5mA flows out of the integrator.

PFD reset is taken off-chip (via R5) thereby incurring a CPLD I/O delay. The 70 pF trimmer is there to explore the effect of adjusting the delay. Close-in phase noise is noticeably reduced when the trimmer is fully meshed. The resultant delay is about 30 ns.

Discrete 1 KHz spurs around a 4353 KHz carrier (N=17, F=0x0100) were reduced by increasing C7 from 1n to 10n. The 1 KHz modulation (clearly visible on the VCO control line) could then be nulled-out by adjusting VR1. The setting was quite critical. Only after doing this was the effect of the trimmer noticeable.

R4/C7 provide a pole at 720 KHz to pre-filter fast edges before they reach the integrator op-amp which has a gain-bandwidth product of only 10 MHz. Arguably, C7 could be increased further. Alternatively, although I haven't tried this, a passive loop filter might be safer, followed by a low frequency op-amp gain buffer. In the RA1792, RACAL used 22Ω / 100 pF and the AD518 op-amp which also has a GBW 0f 10 MHz!

VCO

The VCO is housed in a diecast aluminium box with feedthru capacitors for power and tuning. L1 is 25 turns of No. 22 SWG enameled copper wire on a T68-6 powdered-iron toroid. Ferrite might have been a better choice at this frequency since L1 is sensitive to magnetic fields. Waving a magnetised screwdriver around outside the box has a pronounced effect on the inductance of L1.

I chose a large value for FET biasing resistor R9 to make pinch-off the amplitude limiting mechanism. I kept C9 as small as possible to minimise loading on the tuned circuit.

VCO Isolation Buffer (2 of)

There are two identical isolation amplifers with SMA outputs at opposite ends of the VCO box. The output is no longer sinusoidal since a recent oscillator tweak doubled the amplitude! I added a 50Ω series resistor to stop the emitter followers hard-limiting, but the MOSFETs are still soft-limiting. Harmonics are, at least, a lot easier to remove than phase noise!

The emitter follower operates in class A. The quiescent current must be sufficient to supply the peak load current.

Differential Limiter

This circuit, taken from Rohde[1] (p239), converts the sine(ish) wave from the VCO into a 5V square wave at the CPLD clock input.

References

1. Digital PLL Frequency Synthesizers: Theory and Design Ulrich L Rohde; Prentice-Hall; April 1983; ISBN 0132142392.
2. Sigma Delta Modulation Of A Chaotic Signal Gary Ushaw; University of Edinburgh; October 1996.

Links

My 38-76 MHz and 800-1600 MHz Fractional-N Synthesizers

Fractional-N Synthesizers IFR (formerly Marconi Instruments) application note by David Owen.
An All Digital Fractional-N Synthesizer O. Skydan, UR3IQO, QEX Nov/Dec 2003. Main TO3DSP site.
Behavioural Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits Michael H. Perrott, MIT.
Sigma-Delta Fractional-N Frequency Synthesis Scott Meninger, MIT.
A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise Meninger and Perrott.
Model, Analyze, And Simulate ΣΔ Fractional-N Frequency Synthesizers MICROWAVES & RF DECEMBER 2000.
A New Approach to Fractional-N PLL Design APRIL 2003 MICROWAVE PRODUCT DIGEST.
PFD Dead-zone aka dead-band posted to sci.electronics.design