Huff & Puff VFO Stabiliser

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Huff & Puff stabilisation is a drift-cancellation technique which gives an LC VFO the stability of a PLL synthesizer. The VFO tunes freely until you stop turning the knob, when it snaps to the nearest of many closely-spaced lock points. The first published design was due to the late Klaas Spaargaren PA0KSB in 1973; however, "Technical Topics" April 1969 quotes Peter Martin, G3PDM, outlining the idea. It was refined several times by Klaas and others over the years. Pat Hawker G3VA, the RadCom "Technical Topics" columnist, was the primary disseminator of Huff & Puff information; however, there is now a website where you can read almost everything ever written on the subject: Hans Summers G0UPL has compiled a comprehensive collection of links and scanned articles.

Huff and puff stabilisers come in "slow", "improved" and "fast" varieties. Invented by Peter Lawton G7IXH, using a digital frequency discriminator based on a long shift register, the fast stabiliser corrects higher rates of drift - without compromising lock-point spacing. I built a fast stabiliser using an Altera EPM7064S CPLD. The shift register is implemented as a circular buffer in external SRAM; but, for simplicity, it's drawn as if it were internal to the CPLD in this schematic:

Single-gate buffer U2 improves voltage swing at the integrator input, and isolates it from CPLD power supply noise. The 74HCT part was used because VOH is only 3.2V for this CPLD. U3 is an un-buffered 74HCU part. U3/A drives the CPLD global clock input. The discriminator logic is fully-synchronous.

Coil L2 is a Toko KXNSK4174HM and the tank capacitors are high-Q silver-mica types. As an alternative to VC1, a well-filtered tuning voltage may be applied to the junction of D1 and C5 via a high-value resistor.

To facilitate experimentation, C5 and C9 are mounted on turned-pins removed from DIL sockets. U1, U4 and the oscillator are also socketed.

The integrator needs quite a long time constant for two reasons: to minimise FM modulation on the carrier; and to prevent the stabiliser fighting against deliberate frequency changes! It's interesting to replace C9 with 100n and try to change frequency.

How it works

The square-wave output of the reference oscillator is sampled at the divided VCO clock. Each new sample is compared to a delayed sample emerging from the shift-register. If the shift-register delay spans an integral number of reference cycles, the XOR inputs are always in-phase, and the output is permanently low; if it spans N+½ cycles, the output is permanently high. The average XOR output is a linear function of the fractional number of cycles:

Since the function is averaged over complete cycles, the discriminator is insensitive to phase. The Huff & Puff stabiliser is a frequency-locked-loop (FLL). It evaluates the auto-correlation function of the reference square-wave by a Monte-Carlo statistical method, which relies for its accuracy on the VCO-clocked samples falling evenly throughout the reference cycle:

The XOR output feeds an integrator, the non-inverting input of which is biased at half-rail. Negative feedback adjusts the VCO to keep the average discriminator output at 2.5V. The system moves towards the nearest of many lock points at which there are N+¼ cycles in the shift-register:

In terms of VCO frequency, lock-point spacing (a.k.a. step-size) is given by:

M . Z . fref

Where M = divider modulus; and Z = shift register length. Derivation is left as an exercise for the reader. Hint: express the VCO frequency change required to increase the number of cycles spanned from N to N+1, and eliminate N from your equations as soon as possible. If you want equispaced lock points, reverse the clocks.

Use of socketed components made it easy to re-configure the circuit to check the discriminator's frequency response: the XOR output was fed to a digital voltmeter via a passive low-pass filter; C5 was removed to disconnect the varicap; and the VCO was injection-locked to an external signal generator:

Using a fairly large step size for convenience, a graph of average XOR output against VCO frequency was obtained:

Some designs omit the active integrator, feeding the low-pass filtered XOR output directly to the varicap. This does not regulate average XOR output at half-rail. Instead, points of equilibrium are found where the discriminator slope intersects the temperature-sensitive VCO frequency/voltage characteristic. It's like drawing a load-line on a characteristic curve to find the bias point. Drift is substantially reduced, nevertheless:

Ideally, the reference oscillator duty cycle should be 50%. This can be ensured by inserting a divide-by-2. If the mark-space deviates from 50-50 in either direction, the discriminator output swing won't peak at 5V:

Spectral Purity

One reason for building this experimental circuit was to investigate the spectral purity of the Huff & Puff system. As the XOR output toggles, the varicap tuning voltage slews up and down. This frequency-modulates the carrier. Fortunately, the high clock rate of the discriminator, and the long integrator time constant should minimise the effect. So how pure is the note? It certainly sounds good on an HF receiver; but the spectrum analyzer reveals more:

Stability is excellent and the output is very clean. Only 50 Hz mains hum is evident, and that was to be expected: the experimental circuit was not screened, and there was no on-board regulation. Viewed on the 'scope, via an auxiliary LPF with a short time constant, the 50 Hz is clearly visible on the discriminator output. The first sidebands are 40 dB below the carrier. For an NBFM signal, sideband level in dBc is related to peak phase deviation θp (a.k.a modulation index) by:

Modulating frequency fmod and peak frequency deviation Δf are related to modulation index by:

So, for -40 dBc sidebands, θp = 0.02 and, with a 50 Hz modulating frequency, peak deviation is ±1 Hz.

Step size

A practical VFO for SSB reception requires lock points spaced at most a few tens of Hertz apart. Both a high reference frequency and a long shift register are required. Several published designs use 256-bit shift registers. The 16k-bit SRAM could deliver very small steps; but I am yet to take full advantage of it:

C9 fvco (MHz) fref (MHz) M Z fstep (Hz) Delay (ms) Lock?
10µF4.9766.667262048 2.826n
10µF4.9766.667261024 5.713y
10µF4.9766.667271024 2.826n
10µF4.9766.667252048 5.713y
10µF4.9766.667244096 5.713y
10µF4.9766.667254096 2.826n
10µF4.9732.000254096 5.926n
100µF4.9766.667254096 2.826y
100µF4.9766.667258192 1.453n

I thought 50 Hz pick-up caused these lock failures until, at Peter Lawton's suggestion, I checked the correction rate. The VCO frequency changes by 4 KHz for a 1 volt change in tuning voltage. With C9=10µF, the correction rate is 2.5V / 1MΩ / 10µF * 4KHz/V = 1KHz/second. Feeding this (and 100Hz/s for 100µF) into Peter's simulator predicts all the above observed lock-outcomes. Two things are apparent: the stabiliser continues to operate quite happily in the presence of frequency modulation; and my correction rate is too high for small steps!

SRAM Interface

A little trick I use to equalise CPLD propagation delays is to generate OE using two outputs tied together, tri-stating them and the data bus via LCELLs. This synchronises OE transitions with the data bus drivers. Certain optimisations have to be disabled in the synthesis tool for this to work, as it requires the generation of duplicate logic:

Also shown above is the non-standard JTAG interface: TCLK should really be pulled low; and pin 4 on the JTAG header should be +5V. I suspect my ByteBlaster is getting power through its input protection diodes - but it works!

Logically, the shift register is a bitstream; but the SRAM is organised as bytes. When a bit is updated, the other 7 must be preserved. Bytes are read and re-written on consecutive cycles. The "sample emerging from the shift register" is the old state of the bit being replaced.

CPLD Verilog

The CPLD has 64 macrocells. Short shift registers, up to about 50 stages, can be accomodated without using the external SRAM.