Transmitter Receiver
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| Transmitter |
Receiver |
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| Underneath | Underneath |
In 1993, Electronics and Wireless World published an article [1] by James A. Vincent describing a direct sequence spread spectrum (DSSS) voice link, which remains one of the most accessible/readable introductions to the subject. Daniel Kraus and Walery Maksymiuk (see links) have built versions of James' design. In this, my first experiment with DSSS, I have simplified it using programmable logic devices, and replaced the early / late IF channels with a single "dithered" IF.
James and Walery described UHF radio links with RF power amplification at the transmitter, and complete receiver front-ends including LNA and down-converters. My "transmitter" is actually just a modulator driven by a signal generator, my "receiver" is really only a DSSS IF strip, and they are linked through a length of coax. There's no need to insert attenuation in the channel when experimenting with receiver sensitivity: the carrier input to the modulator can be adjusted down to very low levels at the signal generator.
Two further macrocells are employed in the delta-modulator which converts the analogue audio input into a digital bit sequence, DATA:
The LM324 socket is empty in the photograph. Much of the time during development, the DATA signal was either tied to ground, or fed by a square-wave from the 4040 divider.
In addition to its role as delta-modulator comparator, the LM324 also provides pre-amplification and speech processing. U1A is the pre-amp; Q1 controls the gain of U1C; D1/C2 form a peak detector; and, within the tight constraint of a single 5V supply, U1B extends the input dynamic range over which compression is effective:
The VOGAD (voice operated gain adjusting device) or speech-compressor circuit is based on a design [2] by Lawrence Mayes, who gives an excellent explanation on his website of how the JFET is used here as a voltage-variable-resistor, and shows mathematically how R5/R6 make the drain/source resistance linear. Whilst Lawrence connected the JFET source to the op-amp summing junction, I have adapted the circuit by connecting the JFET the other way around, with source at R2/C1 junction, to work from a single supply. R12 and R13 bias the outputs into Class-A to prevent crossover distortion.
DATA and PRBS are combined in an XOR gate which drives an SBL-1 double-balanced mixer to spread a 70 MHz carrier. Here are four views of the transmitter output spectrum. Note signs of code imbalance in the deep troughs, and imperfect carrier supression at 70 MHz:
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The receiver acquires code-lock on input signals down to approximately -60 dBm. The 70 MHz input is first de-spread in an SBL-1 mixer, then down-converted to 6 MHz using a BF981 dual-gate MOSFET mixer. I originally operated the SBL-1 as a heterodyne-correlator, de-spreading and down-converting to 6 MHz in one go. I pre-mixed the PRBS with the 64 MHz LO using a 74F86 XOR gate which then switched the mixer. It worked; but de-spreading was poor. As a legacy of this, the 64 MHz LO signal is a square wave from a canned DIL oscillator module.
Instead of three channels (early, late and punctual) my receiver has only dithered and punctual. Dithered alternates between early and late at approximately 8 KHz. The early / late sample-and-hold outputs correspond to the independent early / late RSSI outputs in the 3-channel designs. Full-length 127-bit sequences are repeated twice (e.g. Early-Early-Late-Late) and the associated sample-and-hold gates close only during the second repetition. The whole cycle repeats at 4.096 MHz ÷ 127 ÷ 4 = 8.063 KHz.
The early / late RSSI signals feed a differential-input lead-lag loop filter which controls the receiver chip-rate VCXO. As ever, I designed the loop filter using SCILAB. Here's the code. For a 4.096 MHz chip rate, an 8.192 MHz clock is required to produce ± ½ chip delay between early / late and punctual. The operation of the DLL (delay locked loop) is described in [1] James A. Vincent's article. My use of dither, to reduce the number of channels from three to two, should not be confused with the Tau-Dither method, which requires only one channel.
By breaking the loop, connecting the 'scope vertical channels to early and late in A-B differential mode, and adjusting the VCXO trimmer so the receiver code clock rapidly slid past the transmitter code - giving a fast display refresh, I was able to photograph the composite auto-correlation function:
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The advantage of an FM IF chip like the NE604, with a logarithmic RSSI, is you get good dynamic range without needing AGC; the disadvantage is that the composite correlation function peak is rounded and compressed, and low-level noise is disproportionately exaggerated along the baseline.
Punctual IF limiter output is lightly coupled, via 2.2pF capacitor C3, into a 12 MHz oscillator which is injection-locked to the 2nd harmonic. Frequency doubling is equivalent to squaring and removes the modulation. Division by 2 recovers the supressed carrier with a 180 degree phase uncertainty (initial flip-flop state is random). XOR'ing BPSK with recovered carrier yields DATA (or inverted DATA).
BPSK = m(t).cos ωt = ±cos ωt
2nd Harmonic = cos 2ωt = 2cos2ωt - 1
I'm not happy with this front-end: I wanted to terminate all SBL-1 ports in 50 ohms; however, the noise floor was slightly lower after I increase R4 and R8 to 330 ohms. With another resistor, I could attenuate the switching current and present a match. I'm tempted to remove R1 and R9, because the Q of the input tanks is very low; and the L/C ratio looks wrong!
L2 = 2.5 turns of 22 SWG tinned copper wire, tapped 0.5 turns from the cold end.
T1 = Toko KACSK3894 with extra parallel-C to lower the resonant frequency from 10.7 to 6 MHz.
16 KBS Full Duplex Spread Spectrum Receiver RF Data Link Dan Doberstein, DKD Instruments.
Physical Layer Design for a Spread Spectrum Wireless LAN Guoliang Li.
| Copyright © Andrew Holme, 2006. |
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