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This apparatus measures phase noise down to wideband noise floor levels below -170 dBc/Hz. Historically, such measurements were either difficult or expensive to make. Based on the work  of Grove et al., the method described here is cheap, sensitive, accurate and requires no calibration. It is a differential measurement between a device under test (DUT) and a reference oscillator, which are connected to the SMA ports at the extreme left. Ideally, the reference oscillator should be an order of magnitude (or more) quieter, so DUT noise predominates.
The largest board is a Xilinx SP605 FPGA evaluation kit, attached to which (by the FMC connector) is a Linear Technology DC1525A-A quad ADC evaluation board, minus its top-right corner. The two identical boards to which the DUT and reference are connected are custom-made power splitters, feeding four ADC inputs through coaxial cables. The part-populated yellow board, spare from my GPS project, was re-purposed as a clean power supply for a Crystek CPRO33-77.760 crystal oscillator, which can just be seen mounted vertically on the ADC clock input SMA.
ADC resolution is 14-bits.
Samples are received by the FPGA on eight LVDS pairs, each of which can run at up to 1Gbps.
In the FPGA, the four ADC channels are digitally down-converted to IQ complex baseband, low pass filtered, decimated, and phase-demodulated using a CORDIC arc-tangent block.
The resultant phase data is streamed to a Windows laptop via UDP over Ethernet.
Phase data is converted to power spectral density by Fast Fourier Transform (FFT) and displayed in real-time.
The quality of the measurement is refined by correlation / averaging the longer it runs.
The inputs are down-converted by mixing with a quadrature NCO. NCO rate is set close to input frequency, but cannot remain exactly equal, so the baseband signal is close to but rarely at zero frequency. The CORDIC output is phase noise superimposed on a gentle linear ramp, the gradient of which depends on the small unavoidable difference between input frequency and NCO rate.
The first neat trick is to make a differential measurement between DUT and reference, by subtracting their phases. The phase noise of the sampling clock is cancelled-out. The quality of the measurement depends on the reference, not the ADC clock, which can be slightly inferior. Although phases are subtracted, uncorrelated noise powers add. The result is the sum of DUT and reference noise. The reference can be an order of magnitude quieter than the DUT, or, if two identical oscillators are compared, half the power (-3dB) can be attributed to each.
Cancelling clock noise still leaves ADC quantisation noise and thermal noise, which raise the noise floor above -150 dBc/Hz, as already mentioned.
The second neat trick is to duplicate the measurement.
This is the reason for the power splitters.
Everything in the FPGA (and downstream in software) is replicated.
We simultaneously make two completely independent measurements.
Both contain the same (correlated) DUT+Reference noise; but different (uncorrelated) ADC noises.
The latter are then greatly attenuated using the cross spectrum experimental method described in  by E. Rubiola and F. Vernotte.
DUT and reference do not have to be the same frequency. If the sampling points of all four ADC channels are displaced by a small time offset Δt due to jitter on the common sampling clock, it affects the measured phases in proportion to their frequencies: Δθ = ω.Δt. Reference phase must be scaled by the DUT/REF frequency ratio to cancel clock jitter. ADC noises remain uncorrelated, scaled or not. It can be beneficial to use a higher reference frequency, because its phase noise contribution, ΦREF, will then be scaled down. All we want from it is stability.
Differentiation converts sin(ωm.t) to ωm.cos(ωm.t) so has gain j.ωm. The 90 degree phase shift doesn't affect power. Modulating frequency f = ωm/2π is the offset from the carrier.
ADC sampling rate is 77.76 Msps, decimated to 607.5 ksps in the FPGA. FFT length is typically 1000 points, and bins 10 to 99 are plotted from each decade. Length can be increased to get finer detail. Bins LEN/100 to LEN/10 are always plotted in the middle decades; but more are required (up to LEN * 100/607.5) in the first stage to reach 100 kHz. Fewer are needed in the last stage because the graph starts from 0.1 Hz. Low pass filters are 6th order Butterworth IIR with a normalised cut-off frequency of 20/1000.
Results must be scaled to compensate for CIC pass-band droop; differentiator and LPF gain; FFT growth; FFT bin size (converting to dB/Hz) and equivalent noise bandwidth (leakage) of a raised cosine window function, which is applied before the FFT. For efficiency, combined adjustments are pre-computed in dB and applied as offsets to the final outputs.
The same signal can be fed to both the DUT and reference inputs with a third power splitter. I used this configuration to estimate system noise floor, before I knew about the imaginary part of the averaged cross-product. When I started making differential measurements, I discovered another problem: low-frequency spurs, due to crosstalk, at the DUT - Reference difference frequency. Fortunately, although they are quite noticeable in the imaginary part of the cross-product, these spurs barely push through into the real part.
The Wenzel 500-03220 is about 1 Hz off-frequency, judging by the low-frequency crosstalk spurs around 1 and 2 Hz, which are evident in three plots, most strongly in the imaginary part. All plots have spurs at the 50 Hz power line frequency. Harmonics of 50 Hz and other "real" spurs are visible on the synthesizer plots. The -160 dBc spur around 21 kHz in (a) is 77759000*58 - 5000001*902. The two Dana 7020 "Digiphase" synthesizers are several years apart in age; but very similar in performance, except #2 has a probem at 410 Hz. Their closed loop responses match figure 26-8 in Garry Gillette's essay on page 290 of "Analog Circuit Design" edited by Jim Williams. Digiphase close-in performance (-90dBc/Hz @ 1Hz) beats the Marconi 2019A by 20dB. The 2019A has a lower wide band noise floor and much narrower PLL loop bandwidth. Wenzel may be as responsible as Dana for the measurements at 0.1 Hz. The Dana synthesizers were set to 5.000000, so fractional compensation was not operative.
The UI is minimal. The following commands are added to the system menu:
|Load FPGA||Send FPGA configuration bitstream|
|Settings||Edit network addresses and CLK/DUT/REF frequencies|
|Levels||Check ADC input amplitudes|
|Show floor||Toggle display of cross-product imaginary part|
|Stop||Stop and output results (to freq.txt)|
Destination IP and MAC addresses in the Settings dialog are those of the PC and must be correct. The MAC is automatically populated when a local IP is chosen from the drop down. Any free UDP port can be used. Source addresses for the SP605 must also be entered; but are less critical. Only direct cable connections have been tested. It might be possible to go through a switch or router; but packet loss or re-ordering cannot be tolerated. Heavy network or CPU-intensive activities are best avoided whilst performing measurements.
Data is crudely plotted in real-time, then dumped to a file, from which the below-linked Python script produces proper graphs like the above. Hold down the shift key whilst resizing the window to change the number of horizontal and/or vertical decades visible in the real-time view. Resize normally afterwards to re-centre the view. The dBc/Hz power spectral density plot is normalised to 1 Hz bandwidth. Click near a spur to display its frequency and true amplitude in dBc.
The most significant bits of the detected product are zero when the loop is locked, but less significant bits are noisy, and were routed out via a DAC to view the residual noise on an oscilloscope. It was the PLL method of phase noise measurement, implemented digitally. I googled "digital phase noise measurement" and found the Grove et al. paper.
|Copyright © Andrew Holme, 2017.|