Direct digital phase noise measurement
This apparatus measures phase noise down to wideband noise floor levels below -170 dBc/Hz.
Historically, such measurements were either difficult or expensive to make.
Based on the work  of Grove et al., the method described here is cheap, sensitive, accurate and requires no calibration.
It is a differential measurement between a device under test (DUT) and a reference oscillator, which are connected to the SMA ports at the extreme left.
Ideally, the reference oscillator should be an order of magnitude (or more) quieter, so DUT noise predominates.
The largest board is a Xilinx SP605 FPGA evaluation kit, attached to which (by the FMC connector) is a Linear Technology DC1525A-A quad ADC evaluation board,
minus its top-right corner.
The two identical boards to which the DUT and reference are connected are custom-made power splitters, feeding four ADC inputs through coaxial cables.
The part-populated yellow board, spare from my GPS project,
was re-purposed as a clean power supply for a Crystek CPRO33-77.760 crystal oscillator, which can just be seen mounted vertically on the ADC clock input SMA.
ADC resolution is 14-bits.
Samples are received by the FPGA on eight LVDS pairs, each of which can run at up to 1Gbps.
In the FPGA, the four ADC channels are digitally down-converted to IQ complex baseband, low pass filtered, decimated, and phase-demodulated using a CORDIC arc-tangent block.
The resultant phase data is streamed to a Windows laptop via UDP over Ethernet.
Phase data is converted to power spectral density by Fast Fourier Transform (FFT) and displayed in real-time.
The quality of the measurement is refined by correlation / averaging the longer it runs.
The inputs are down-converted by mixing with a quadrature NCO.
NCO rate is set close to input frequency, but cannot remain exactly equal,
so the baseband signal is close to but rarely at zero frequency.
The CORDIC output is phase noise superimposed on a gentle linear ramp,
the gradient of which depends on the small unavoidable difference between input frequency and NCO rate.
Cancel & correlate
It's possible to measure phase noise of a DUT, relative to the sampling clock, using a single ADC channel.
In fact, I did so as a first step.
So why the two inputs and four ADC channels?
Because using a single 14-bit ADC, even assuming zero sampling clock jitter, the simulation-predicted noise floor is worse than -150 dBc/Hz.
Typically, more like -140 dBc/Hz.
Grove et al. did two things to get the noise floor down below -170 dBc/Hz.
The first neat trick is to make a differential measurement between DUT and reference, by subtracting their phases.
The phase noise of the sampling clock is cancelled-out.
The quality of the measurement depends on the reference, not the ADC clock, which can be slightly inferior.
Although phases are subtracted, uncorrelated noise powers add.
The result is the sum of DUT and reference noise.
The reference can be an order of magnitude quieter than the DUT,
or, if two identical oscillators are compared, half the power (-3dB) can be attributed to each.
Cancelling clock noise still leaves ADC quantisation noise and thermal noise, which raise the noise floor above -150 dBc/Hz, as already mentioned.
The second neat trick is to duplicate the measurement.
This is the reason for the power splitters.
Everything in the FPGA (and downstream in software) is replicated.
We simultaneously make two completely independent measurements.
Both contain the same (correlated) DUT+Reference noise; but different (uncorrelated) ADC noises.
The latter are then greatly attenuated using the cross spectrum experimental method described in  by E. Rubiola and F. Vernotte.
DUT and reference do not have to be the same frequency.
If the sampling points of all four ADC channels are displaced by a small time offset Δt due to jitter on the common sampling clock,
it affects the measured phases in proportion to their frequencies: Δθ = ω.Δt.
Reference phase must be scaled by the DUT/REF frequency ratio to cancel clock jitter.
ADC noises remain uncorrelated, scaled or not.
It can be beneficial to use a higher reference frequency, because its phase noise contribution, ΦREF, will then be scaled down.
All we want from it is stability.
The 32-bit fixed-point binary output of the CORDIC is encoded in semi-circles with 31 bits after the binary point.
The most significant bit represents ±1 semi-circle or ± π radians.
The angle can be interpreted as signed or unsigned, without ambiguity.
Due to unavoidable frequency differences, the measured phases will always be slowly but steadily ramping, either up or down.
Phase 'wraps' occur every 2π radians.
Real measurements have phase noise superimposed on the ramp and can "chatter" back and forth several times as they go through the wrapping point:
These discontinuities must be removed before the FFT.
One way is to unwrap them.
Integer precision can be extended before the binary point and 1.0 circles (2.0 semi-circles) are added or subtracted every time the raw data wraps.
Another way - the method I am using - is to convert phase to instantaneous frequency, ω, by differentiating.
Each phase wrap generates a carry or a borrow from the differentiator;
but there are no jumps or glitches in its 32-bit output.
The FFT then calculates power spectral density (PSD) of frequency fluctuation, which is transformed to PSD of phase afterwards.
An ideal differentiator converts sin(ωt) to ω.cos(ωt) and so has gain ω.
The 90 degree phase shift doesn't affect power.
Originally, LivePlot divided output bins by ω² to obtain PSD of phase;
however, this caused a slight droop in wideband noise floors approaching Nyquist,
where gain of the first-difference digital differentiator deviates from ideal.
This small inaccuracy was corrected in LivePlot version 16 by using actual gain of the digital differentiator instead of ω.
The final output, ℒ(f), is half (one side band) of the power spectral density of phase, relative to the carrier, in dBc/Hz.
This is plotted on a log/log scale, typically over the frequency range 0.1 Hz to 100 kHz.
Samples are transformed into the frequency domain by Fast Fourier Transform.
Making two independent measurements doubles the amount of processing required.
In order to execute this in real-time, with the same number of data points in each decade,
the processing is broken up into a succession of identical stages, decimating by 10 at each step:
The above diagram includes cross-correlation.
Complex FFT outputs bins from one measurement are multiplied by the complex conjugate of the corresponding bin from the other.
The complex product is averaged for minutes, hours or days.
Uncorrelated noises are attenuated by 5log10(N) where N is the number averaged.
After a while, the average real part tends to contain only correlated noise.
The average imaginary part is an indicator of system noise floor.
5dB steps can been seen in the imaginary part between decades because of decimation.
Each decade averages 10 times more data than the next lower in frequency.
ADC sampling rate is 77.76 Msps, decimated to 607.5 ksps in the FPGA.
FFT length is typically 1000 points, and bins 10 to 99 are plotted from each decade.
Length can be increased to get finer detail.
Bins LEN/100 to LEN/10 are always plotted in the middle decades;
but more are required (up to LEN * 100/607.5) in the first stage to reach 100 kHz.
Fewer are needed in the last stage because the graph starts from 0.1 Hz.
Low pass filters are 6th order Butterworth IIR with a normalised cut-off frequency of 20/1000.
Results must be scaled to compensate for CIC pass-band droop; differentiator and LPF gain; FFT growth; FFT bin size (converting to dB/Hz) and equivalent noise bandwidth (leakage) of a raised cosine window function, which is applied before the FFT.
For efficiency, combined adjustments are pre-computed in dB and applied as offsets to the final outputs.
Does this sounds too good to be true?
Are you wondering what the snag is?
The biggest problem is instrument-generated spurs, due to ADC quantisation.
These appear when harmonics of the input signal fall close to harmonics of the sampling clock.
I discovered them the hard way.
The DC1525A ADC board works up to 125 Msps and I was making measurements of 5 MHz sources using a 124.998 MHz sampling clock!
None of the papers I read beforehand led me to expect this, and I was puzzled for a while, until I reproduced the spurs using a very simple simulation.
Moving to 77.76 Msps improved matters.
The same signal can be fed to both the DUT and reference inputs with a third power splitter.
I used this configuration to estimate system noise floor, before I knew about the imaginary part of the averaged cross-product.
When I started making differential measurements, I discovered another problem:
low-frequency spurs, due to crosstalk, at the DUT - Reference difference frequency.
Fortunately, although they are quite noticeable in the imaginary part of the cross-product, these spurs barely push through into the real part.
Each of the plots below was averaged over several hours.
DUT and reference inputs were 5 MHz.
Blue trace is ℒ(f), the one-sided power spectral density of phase,
as estimated by the real part of the average cross-product.
Green trace is system noise floor in the imaginary part.
The Wenzel ULN is an ultra-low-noise reference oscillator:
The Wenzel 500-03220 is about 1 Hz off-frequency,
judging by the low-frequency crosstalk spurs around 1 and 2 Hz, evident most strongly in the imaginary part.
All plots have spurs at the 50 Hz power line frequency.
Harmonics of 50 Hz and other "real" spurs are visible on the synthesizer plots.
The -160 dBc spur around 21 kHz in (a) is 77759000*58 - 5000001*902.
The Dana 7020 "Digiphase" synthesizer's closed loop response matches figure 26-8 in Garry Gillette's essay on page 290 of "Analog Circuit Design" edited by Jim Williams.
My 2019A takes time to warm-up before delivering this performance.
Notice how it selects a narrower loop bandwidth when modulated.
Peak phase deviation of 0.001 radians is -66 dBc.
Spur amplitudes cannot be read directly off the dBc/Hz scale.
The plot is scaled by FFT bin size to normalised power spectral density in a 1 Hz bandwidth.
Clicking on a spur in the GUI reveals its true amplitude.
LivePlot reports 5.81 kHz and -66.3 dBc.
Break through from the audio oscillator is observable with modulation disabled.
Software - Updated October 2019
Windows 10 can be used with a workaround; but Windows 7 or XP is recommended.
The software has been built successfully with Visual Studio 6, Visual Studio 2013 and Visual Studio 2019.
Source files and installation instructions can be found in a zip linked below.
The UI is minimal.
The following commands are added to the system menu:
|Load FPGA ||Send FPGA configuration bitstream|
|Settings||Edit measurement frequencies, network settings e.t.c. |
|Levels ||Check ADC input amplitudes|
|Start ||Start measurement|
|Stop ||Stop and output results (to csv file)|
The IP address of the PC must be specified on the Settings dialog Ethernet tab.
Only direct cable connections have been tested.
It might be possible to work through a switch or router;
but packet loss and re-ordering cannot be tolerated.
Heavy network or CPU-intensive activities are best avoided whilst performing measurements.
Data is crudely plotted in real-time,
then dumped to a file, from which the below-linked Python script produces proper graphs like the above.
Hold down the shift key whilst resizing the window to change the number of horizontal and/or vertical decades visible in the real-time view.
Resize normally afterwards to re-centre the view.
The dBc/Hz power spectral density plot is normalised to 1 Hz bandwidth.
Click near a spur to display its frequency and true amplitude in dBc.
Left-click for PN spurs; right-click for AN.
Verilog - Updated October 2019
The software zip contains a pre-generated bit stream in XSVF format for the "Load FPGA" menu option.
The FPGA has been built successfully using Xilinx ISE 13.3 and 14.7.
Project files can be found in a zip linked below.
The build procedure is:
open QuadChannel.xise project;
migrate to 14.7 if necessary;
locate and select fifo - fifo_generator_v8_3 in the hierarchy list;
run "Regenerate Core" in the process list;
scroll back up and click on top-level module QuadChannel.v in the hierarchy;
run "Generate Programming File" in the process list.
- 8-lane LVDS source-synchronous deserializer
- Interpolating quadrature NCO
- Parameterised CIC filter
- CORDIC arc-tangent function
- UDP Ethernet sender
- 32x32 and 14x34 multipliers
I wish to thank Joël Imbaud of Institut FEMTO-ST who replicated the SP605/DC1525A setup and verified its accuracy against a commercial Symmetricom 5120A.
Instead of custom boards, Joël used Mini-Circuits attenuators; ZMSC-2-1+ connectorized power splitters; SPB10.7+ and SLP5+ filters; and AMP-77 amplifiers.
He removed the SFP cage to avoid sawing his ADC board.
I checked the Gerbers before cutting mine.
I also wish to thank Adrian Rus who obtained good agreement between his SP605 / DC1525A and a Rohde and Schwarz FSWP for one Wenzel ULNO;
and against the manufacturer's specification of another.
Adrian measured DUT noise of -176 dBc/Hz with a system noise floor below -180 dBc/Hz after cross correlation.
He tested many ways of feeding the ADC and recommends this configuration for minimising artifacts such as negative bias, and reaching ultra-low noise floors, even when measuring low output level DUTs:
Two high-quality reference oscillators are connected directly (via attenuators) to the ADC inputs.
Their noises are removed by cross-correlation and the measurement is DUT noise only.
Adrian modified the 1525A clock input to accept sinusoidal drive and reduced clock noise by soldering 50Ω resistors across the ADC inputs.
He found 6dB resistive splitters superior to 3dB reactive types.
Clean, independent power supplies are mandatory for the amplifiers.
Adrian Rus is co-author of a paper  entitled "Artifacts and Errors in Cross-Spectrum Phase Noise Measurements"
concerning how the thermal energy of the power splitter has opposite phases on the two DUT channels, producing an anti-correlated bias,
leading to artificially low measurements of b0 wideband noise.
My power splitter schematic is linked below.
The design is not ideal for measuring ultra-low noise floors.
It was a first attempt based on guess work.
Primarily, I wanted anti-alias filters, around which I placed resistive attenuators for wideband impedance matching.
MMIC amplifiers restore the level and provide reverse isolation.
Unfortunately, the amplifiers and attenuators compromise overall noise figure.
Input configuration is best optimized by trial and error using SMA connectorized modules.
I tried Adrian's approach of using not one but two reference oscillators, connected directly to the ADC inputs, with no filters and no amplifiers;
and a DUT connected via just a Mini-Circuits PSC 3dB reactive splitter, again with no filters or amplifiers.
This worked well and allowed me to reach a lower broadband noise floor.
My custom splitter boards were probably a bad idea.
I wish to thank George Korga for highlighting a problem with FPGA version 8.1 and helping me fix it and get some interesting insights.
George has been pushing the limits of the instrument by over-clocking the ADC, and testing DUT frequencies in the 2nd Nyquist zone.
Clock jitter cancellation only worked if the DUT/REF ratio was less than 8.
My unnecessary use of signed arithmetic for the reference frequency scaling factor produced the opposite of cancellation if the ratio exceeded this limit.
An updated FPGA version 8.2 is currently available on request supporting DUT/REF < 16.
DUT frequencies in the 2nd Nyquist zone alias to fALIAS=fCLK-fDUT.
True DUT frequency must still be specified in the settings dialog for correct reference scaling, and fNCO=fDUT.
The mixers produce sum and difference products at fALIAS ± fNCO.
The sum product is fCLK which folds to DC (0 Hz) and the difference product is attenuated / removed by the CIC LPF.
November 2021 - LivePlot v13
Software version 13 with the following new features is available below for download:
- Selectable FFT length from 128 to 4096 points: shorter for faster convergence; longer for finer resolution
- Frequency points plotted in geometric progression (equi-spaced on log scale) to reduce "bunching"
- Timer shows elapsed measurement time or counts down and stops
- Uses x87 80-bit double extended-precision floating-point for inter-stage decimation filters and Sxy averaging
- Steeper filter roll-off allowing use of more FFT bins per decade
- Settings dialog accessible whilst measurement in progress.
Read more HERE about my attempts to verify the specification of a Wenzel ULNO using the dual reference or "3-cornered-hat" method,
including custom amplifiers and non-reflective filters.
May 2022 - LivePlot v16
- LogFFT.cpp code polishing to (hopefully) improve readability.
- 16-byte buffer alignment ensures deterministic FFTW algorithm selection.
- Fixes 3 dB up-tick at Nyquist due to CIC filter first alias.
- Fixes slight droop in wideband noise floor level, as explained under Phase wraps above.
September 2022 - LivePlot v17
LivePlot v17 and FPGA firmware v9 measure phase noise out to a maximum offset frequency of 1 MHz.
FPGA decimation rate is now switchable between 128 and 64.
Please refer to the release notes for full details of this and other improvements.
December 2022 - LivePlot v18
Rob van Cann has measured microwave synthesizers
by down-converting the DUT, after splitting, to an IF within ADC range,
mixing with local oscillators uncorrelated at offsets of interest
but locked in a narrow loop bandwidth to prevent drift and spur smearing.
Rob sometimes uses LOs above and below DUT frequency, creating anti-correlation, for which a Negate Sxy option was added to the settings dialog.
DUT frequency is specified as the IF.
Use of 2(1-cos(ωT)) to compute differentiator gain suffered loss of precision causing division by zero at extremely close-in offsets.
This is fixed by using (2sin(ωT/2))2 instead.
February 2023 - LivePlot v19
LivePlot v19 and FPGA firmware v10 configure the ADC in 2-lane 14-bit mode.
The default 16-bit mode used by previous versions of LivePlot pads each frame with unused bits.
I have detected errors on ADC channel 2 pushing 16-bit mode above 130 Msps.
Reducing the bit rate by 12.5% makes it reliable when over-clocking the ADC.
Schottky diode multipliers can scale-up PN by a precise amount,
without adding significant noise themselves.
A multiplier option has been added on the bias tab which subtracts 20*log10(M) from the PN plot.
True DUT frequency before multiplication must be entered on the measurement tab.
Bug fixes: version 19 allows frequency entry to 1 Hz precision without rounding; Negate Sxy no longer applied to AN plot.
March 2023 - LivePlot v20
LivePlot applies the raised cosine window to prevent FFT spectral leakage.
LivePlot v20 optionally uses a 50% overlap.
In v19 and earlier, samples in the tails of the window function had little influence.
With overlapping enabled: every sample is used twice, window peaks align with tails, halfway points align, and every sample has equal net weight.
Overlapping doubles the number of correlations averaged in a given measurement time, causing the plot to smooth more quickly.
Here is a 6-second simulated measurement of b0 = -170 dBc/Hz white phase on v19:
And here the same simulated data processed by v20 with overlap enabled in the settings dialog:
April 2023 - LivePlot v21
LivePlot v21 and FPGA firmware v11 add a new menu option "Frequencies..."
which measures by linear regression the phase slope of best fit of the four ADC channels (relative to the ADC clock)
and optionally saves raw phase data to disk for post processing.
Data format is 16 bytes per sample (32-bits per channel) at the decimated (by 64 or 128) rate, taken directly from the CORDIC outputs.
Bit 31 represents -π radians.
LivePlot v21 and FPGA firmware v11 also fix an intermittent bug that was introduced in firmware v10 with the change to using ADC 2-lane 14-bit mode.
Very occasionally, v10 would stop sending Ethernet data and report the level of one or more channels as -100% (minus) until the firmware was reloaded.
The fix is to disable the FPGA PLL which receives the ADC clock until the ADC has been fully configured.
By default, the ADC outputs a double rate clock which reaches the FPGA fabric in v10.
I saw the symptoms twice whilst developing v21 and was eventually able to reproduce them at will.
Independent decimation counters in the CIC I/Q low pass filters got out of sync.
An interlock squashes the data valid signal if all eight are not aligned.
They are now reset at the start of every measurement.
May 2023 - LivePlot v22
LivePlot v22 supports overlapped ADEV.
Raw instantaneous frequency data is taken after decimation filters in each arm of the PN signal path.
The tapping point, selected on the ADEV tab in the Settings dialog, determines bandwidth fH and Τ0.
Frequency differences fDUT1-fREF1 and fDUT2-fREF2 are used.
Cross variance is computed and averaged at octave-spaced points.
A settings dialog radio button switches the screen display between PSD and ADEV view.
Results are written to Allan.csv, which can be plotted using a new Python script.
Here is ADEV measured in red and calculated from a PSD truncated to the same bandwidth in teal:
LivePlot v22 requires FPGA firmware v12, which includes a frequency counter for measuring ADC clock.
The ADC supplies two LVDS clocks: FR and DCO.
The firmware has always only used FR and until v12 did not provide an LVDS differential termination on the unused DCO pair!
It was sad to hear the news recently that Analog Devices have discontinued the DC1525A-A evaluation board.
This project has slowly but steadily gained users worldwide over the years, but the hardware can no longer be sourced off-the-shelf.
One option might be an open-source board.
It may be prudent to switch ADC chip.
The 16-bit AD9653 is pin compatible with their AD9253 14-bit and AD9633 12-bit parts.
July 2023 - LivePlot v23
A small ADEV fix to prevent display and output of points where the mean covariance is negative.
This project began with an attempt to make very precise average frequency measurements using a digital PLL.
Sampling at 1 Msps, using the 14-bit ADC on the Spartan 3E Starter Kit, it was possible to measure average frequency of a 100 kHz source to µHz precision over a 1 second averaging period:
In order to measure exactly 100000.000000 Hz, the ADC was clocked using a standard frequency output from the same generator that produced the 100 kHz.
Despite this, a small frequency offset was observed as the equipment warmed-up.
This was due to a time-varying delay (phase shift) in the signal path, equivalent to a frequency shift ω = dθ/dt, which settled down once thermal equilibrium was reached.
The most significant bits of the detected product are zero when the loop is locked,
but less significant bits are noisy, and were routed out via a DAC to view the residual noise on an oscilloscope.
It was the PLL method of phase noise measurement, implemented digitally.
I googled "digital phase noise measurement" and found the Grove et al. paper.
* The v12 installation instructions explain how to setup FFTW and Xilinx JTAG.
Those bits still apply; however, contrary to what the document says:
you don't need to build the Windows executable yourself any more because you can just download the pre-built binary.
1. Grove, J. et al., "Direct-digital phase-noise measurement," Proc. of 2004 IEEE International Frequency Control Symposium, Montreal, Canada, pp. 287-291, August 2004.
2. E. Rubiola and F. Vernotte, "The cross-spectrum experimental method," Mar. 2010, arXiv:1003.0113v1 [physics.ins-det].
3. Y. Gruson, A. Rus, U. L. Rohde, A. Roth and E. Rubiola "Artifacts and Errors in Cross-Spectrum Phase Noise Measurements," Mar. 2020, arXiv:1912.10449 [physics.ins-det].