|Back to projects|
This apparatus measures phase noise down to wideband noise floor levels below -170 dBc/Hz. Historically, such measurements were either difficult or expensive to make. Based on the work  of Grove et al., the method described here is cheap, sensitive, accurate and requires no calibration. It is a differential measurement between a device under test (DUT) and a reference oscillator, which are connected to the SMA ports at the extreme left. Ideally, the reference oscillator should be an order of magnitude (or more) quieter, so DUT noise predominates.
The largest board is a Xilinx SP605 FPGA evaluation kit, attached to which (by the FMC connector) is a Linear Technology DC1525A-A quad ADC evaluation board, minus its top-right corner. The two identical boards to which the DUT and reference are connected are custom-made power splitters, feeding four ADC inputs through coaxial cables. The part-populated yellow board, spare from my GPS project, was re-purposed as a clean power supply for a Crystek CPRO33-77.760 crystal oscillator, which can just be seen mounted vertically on the ADC clock input SMA.
ADC resolution is 14-bits.
Samples are received by the FPGA on eight LVDS pairs, each of which can run at up to 1Gbps.
In the FPGA, the four ADC channels are digitally down-converted to IQ complex baseband, low pass filtered, decimated, and phase-demodulated using a CORDIC arc-tangent block.
The resultant phase data is streamed to a Windows laptop via UDP over Ethernet.
Phase data is converted to power spectral density by Fast Fourier Transform (FFT) and displayed in real-time.
The quality of the measurement is refined by correlation / averaging the longer it runs.
The inputs are down-converted by mixing with a quadrature NCO. NCO rate is set close to input frequency, but cannot remain exactly equal, so the baseband signal is close to but rarely at zero frequency. The CORDIC output is phase noise superimposed on a gentle linear ramp, the gradient of which depends on the small unavoidable difference between input frequency and NCO rate.
The first neat trick is to make a differential measurement between DUT and reference, by subtracting their phases. The phase noise of the sampling clock is cancelled-out. The quality of the measurement depends on the reference, not the ADC clock, which can be slightly inferior. Although phases are subtracted, uncorrelated noise powers add. The result is the sum of DUT and reference noise. The reference can be an order of magnitude quieter than the DUT, or, if two identical oscillators are compared, half the power (-3dB) can be attributed to each.
Cancelling clock noise still leaves ADC quantisation noise and thermal noise, which raise the noise floor above -150 dBc/Hz, as already mentioned.
The second neat trick is to duplicate the measurement.
This is the reason for the power splitters.
Everything in the FPGA (and downstream in software) is replicated.
We simultaneously make two completely independent measurements.
Both contain the same (correlated) DUT+Reference noise; but different (uncorrelated) ADC noises.
The latter are then greatly attenuated using the cross spectrum experimental method described in  by E. Rubiola and F. Vernotte.
DUT and reference do not have to be the same frequency. If the sampling points of all four ADC channels are displaced by a small time offset Δt due to jitter on the common sampling clock, it affects the measured phases in proportion to their frequencies: Δθ = ω.Δt. Reference phase must be scaled by the DUT/REF frequency ratio to cancel clock jitter. ADC noises remain uncorrelated, scaled or not. It can be beneficial to use a higher reference frequency, because its phase noise contribution, ΦREF, will then be scaled down. All we want from it is stability.
Differentiation converts sin(ωm.t) to ωm.cos(ωm.t) so has gain j.ωm. The 90 degree phase shift doesn't affect power. Modulating frequency f = ωm/2π is the offset from the carrier.
ADC sampling rate is 77.76 Msps, decimated to 607.5 ksps in the FPGA. FFT length is typically 1000 points, and bins 10 to 99 are plotted from each decade. Length can be increased to get finer detail. Bins LEN/100 to LEN/10 are always plotted in the middle decades; but more are required (up to LEN * 100/607.5) in the first stage to reach 100 kHz. Fewer are needed in the last stage because the graph starts from 0.1 Hz. Low pass filters are 6th order Butterworth IIR with a normalised cut-off frequency of 20/1000.
Results must be scaled to compensate for CIC pass-band droop; differentiator and LPF gain; FFT growth; FFT bin size (converting to dB/Hz) and equivalent noise bandwidth (leakage) of a raised cosine window function, which is applied before the FFT. For efficiency, combined adjustments are pre-computed in dB and applied as offsets to the final outputs.
The same signal can be fed to both the DUT and reference inputs with a third power splitter. I used this configuration to estimate system noise floor, before I knew about the imaginary part of the averaged cross-product. When I started making differential measurements, I discovered another problem: low-frequency spurs, due to crosstalk, at the DUT - Reference difference frequency. Fortunately, although they are quite noticeable in the imaginary part of the cross-product, these spurs barely push through into the real part.
The Wenzel 500-03220 is about 1 Hz off-frequency, judging by the low-frequency crosstalk spurs around 1 and 2 Hz, evident most strongly in the imaginary part. All plots have spurs at the 50 Hz power line frequency. Harmonics of 50 Hz and other "real" spurs are visible on the synthesizer plots. The -160 dBc spur around 21 kHz in (a) is 77759000*58 - 5000001*902. The Dana 7020 "Digiphase" synthesizer's closed loop response matches figure 26-8 in Garry Gillette's essay on page 290 of "Analog Circuit Design" edited by Jim Williams.
My 2019A takes time to warm-up before delivering this performance. Notice how it selects a narrower loop bandwidth when modulated. Peak phase deviation of 0.001 radians is -66 dBc. Spur amplitudes cannot be read directly off the dBc/Hz scale. The plot is scaled by FFT bin size to normalised power spectral density in a 1 Hz bandwidth. Clicking on a spur in the GUI reveals its true amplitude. LivePlot reports 5.81 kHz and -66.3 dBc. Break through from the audio oscillator is observable with modulation disabled.
|Load FPGA||Send FPGA configuration bitstream|
|Settings||Edit measurement frequencies, network settings e.t.c.|
|Levels||Check ADC input amplitudes|
|Stop||Stop and output results (to csv file)|
The IP address of the PC must be specified on the Settings dialog Ethernet tab. Only direct cable connections have been tested. It might be possible to work through a switch or router; but packet loss and re-ordering cannot be tolerated. Heavy network or CPU-intensive activities are best avoided whilst performing measurements.
Data is crudely plotted in real-time, then dumped to a file, from which the below-linked Python script produces proper graphs like the above. Hold down the shift key whilst resizing the window to change the number of horizontal and/or vertical decades visible in the real-time view. Resize normally afterwards to re-centre the view. The dBc/Hz power spectral density plot is normalised to 1 Hz bandwidth. Click near a spur to display its frequency and true amplitude in dBc. Left-click for PN spurs; right-click for AN.
I also wish to thank Adrian Rus who obtained good agreement between his SP605 / DC1525A and a Rohde and Schwarz FSWP for one Wenzel ULNO;
and against the manufacturer's specification of another.
Adrian measured DUT noise of -176 dBc/Hz with a system noise floor below -180 dBc/Hz after cross correlation.
He tested many ways of feeding the ADC and recommends this configuration for minimising artifacts such as negative bias, and reaching ultra-low noise floors, even when measuring low output level DUTs:
Two high-quality reference oscillators are connected directly (via attenuators) to the ADC inputs. Their noises are removed by cross-correlation and the measurement is DUT noise only. Adrian modified the 1525A clock input to accept sinusoidal drive and reduced clock noise by soldering 50Ω resistors across the ADC inputs. He found 6dB resistive splitters superior to 3dB reactive types for isolation and bias. Clean, independent power supplies are mandatory for the amplifiers.
I wish to thank George Korga for highlighting a problem with FPGA version 8.1 and helping me fix it and get some interesting insights. George has been pushing the limits of the instrument by over-clocking the ADC, and testing DUT frequencies in the 2nd Nyquist zone. Clock jitter cancellation only worked if the DUT/REF ratio was less than 8. My unnecessary use of signed arithmetic for the reference frequency scaling factor produced the opposite of cancellation if the ratio exceeded this limit. An updated FPGA version 8.2 is currently available on request supporting DUT/REF < 16.
DUT frequencies in the 2nd Nyquist zone alias to fALIAS=fCLK-fDUT. True DUT frequency must still be specified in the settings dialog for correct reference scaling, and fNCO=fDUT. The mixers produce sum and difference products at fALIAS ± fNCO. The sum product is fCLK which folds to DC (0 Hz) and the difference product is attenuated / removed by the CIC LPF.
The most significant bits of the detected product are zero when the loop is locked, but less significant bits are noisy, and were routed out via a DAC to view the residual noise on an oscilloscope. It was the PLL method of phase noise measurement, implemented digitally. I googled "digital phase noise measurement" and found the Grove et al. paper.
|Copyright © Andrew Holme, 2017.|