Mark 2 FORTH Computer

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Control schematic

U2 and U6 place immediate operands and sign-extended conditional branch offsets on the data bus. U2 forces the high byte to 00H for byte reads.

U9 and U12 are the instruction register (IR)


CPU schematic


Memory schematic

This is the second version of the memory board. The original had no buffering on incoming signals. After the problems I had with contention and glitches, I buffered everything.


I/O schematic

RESET is synchronised to the rising edge of CLK2 to avoid glitches during BUS state transitions. It was reseting the UART until I did this!