Mark 1 FORTH Computer

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These schematics were created using WinSchematic 4.0 Evaluation by CSiEDA which I downloaded from www.csieda.com for free!

In my opinion, this is an excellent piece of software. It is very easy and enjoyable to use. It comes with a huge library of symbols and also has a library editor for creating your own.

I completed all the drawing before a single joint was soldered. This gave me confidence that everything was covered. Ticking off the connections as I went, wiring was a stress-free no-brainer. Afterwards, I buzzed-out every connection and, again, ticked them off as I went.

The original diagrams are in vector format and can thus be scaled to any desired size. In converting them to GIF for the web, I selected a width of 1000 pixels. Download the original hi-res schematics here.

The following were added to answer frequently asked questions:

Original sketch from which diode matrix ROM was pen-wiredDiode matrix.pdf
HC244 buffer is essential. Diode drop exceeds VIL(max) of LS244Diode and pullups.gif
Using LS157 to set function (W or IP) of index register cardsLS157.pdf

Micro code sequencer

Sequencer schematic

U1OP Latch
U2,3,4µ Program Counter (µPC)
U5µ ROM (with pin 26 wired to Vcc, the socket accepts 24 or 28 pin devices)
U6,7µ Latch
U10Conditional test multiplexer
U11µ Bus driver

Instruction Decoder and system clock

Decoder schematic

U8"Zero" register (force 00H on data bus)

Stacks

Stacks schematic

U5,6PSP Parameter stack pointer
U7,8RSP Return stack pointer

I used 28 pin sockets for the RAM chips with a jumper to select 6116 or 6264. I fitted the former but thought it best to support both because the 6116 is hard to source now.

Index Register (2 of)

Index register schematic

The cards also have LS157 Quad 1-of-2 multiplexers for the control inputs. A jumper configures the cards as either W or IP via the LS157 common select input.

Memory

Memory schematic

I have 8K ROM and 24K RAM with only 3 support chips. This card also carries the power-on reset circuit: there was no space for it elsewhere!

I/O

I/O schematic

The I/O card was built and tested before the ALU. I planned to use U4, a hex tri-state inverter, to gate the RXRDY signal onto D0 for conditional tests. Unfortunately, this wouldn't have worked because inputs to the conditional multiplexer must be stable throughout a skip. I had to mount the LS368 on a header with a transparent latch until the ALU was ready! The links to D0 and D1 have now been broken.

I originally hoped to operate the UART in the x1 clock mode giving the option of 38K4, 19K2 or 9600 baud. Unfortunately, reception is only reliable in the x16 and x64 modes. The maximum attainable baud rate, using the x16 mode and the Q4 output of the 4060 divider, is 9600 from a 2.4576MHz crystal.

ALU

ALU schematic

U1F result output
U2A input latch
U3B input latch
U4Function select latch (data from diode matrix ROM)
U5Conditional flags (to multiplexer)
U6IRQ Enable and IRQ flag latch
U9Carry input select MUX
U10Overflow detect